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《STM32H750参考手册_共3289页》介绍
IntroductionThis reference manual targets application developers.It provides complete information onhowto use the STM32H742xx， STM32H 743/53xxandSTM32H750xB microcontrollermemory and peripheralsThe STM32H 742， STM32H 743/753andSTM32H 750 are lines of microcontrollers withdifferent memory sizes， packages and peripherals.For ordering information， mechanical， and electrical device characteristics please refer tothe corresponding datasheets，For information on the Arm Cortex-M7withFPUcore， please refer to the correspondingArm Technical Reference Manuals.
Related documents·Arm°Cortex-M7 Technical Reference Manual， available from www.arm.com.Cortex -M 7 programming manual(PM 0253)STM32H 742/743xxandSTM32H753xx datasheetsSTM32H750xB datasheetDocumentation conventions
《STM32H750参考手册_共3289页》目录
1.1General infrmatin.
1.2List f abbreviatins fr registers
1.3Glssary.
1.4Availability f peripherals.
1.5Availablity f securty features.
Memry and bus architecture
2.1System architecture.
2.2AXl intercnnect matrix(AXIM) .
2.3Memry rganizatin
2.4Embedded SRAM.
2.5Flashmemry verview
2.6Bt cnfiguratin
Embedded Flashmemry(FLASH) .
3.1Intrductin.
3.2FLASH main features.
3.3FLASH functinal descriptin.
advanced Arm-based 32-bit MCUs
RM0433Rev 61/3289
RMD433Rev 6
Aprl 2019
Bus matrices.
TCM buses
Bus-t-bus bridges.
Inter-dmain buses.
CPU buses.
Busmaster peripherals.
Clcks t functinal blcks.
AXl intrductin.
AXl intercnnect main features.
AXl intercnnect functinal descriptin.
AXl intercnnect registers.
AXl intercnnect register map.
Intrductin.
Memry map and register bundary addresses
FLASH blck diagram.
FLASH inte mal signals.
FLASH architecture and integratin in the system.
Flashmemry architecture and usage.
FLASH system perfrmance enhancements.
FLASH data prtectin schemes.
verview f FLASH peratins
FLASH read peratins.
FLASH prgram peratins.
FLASH erase peratins.
FLASH parallel peratins(STM32H 742/743/ 753 devices nly) . 156
Flashmemry errr prtectins.156
Flash bank and register swapping(STM32H 742/743/ 753 devices nly) 158
FLASH reset and clcks.161
Abut ptin bytes.161
ptin byte lading.162
ptin byte mdificatin.162
ptin bytes verview.165
Descriptin f user and system ptin bytes.167
Descriptin f data prtectin ptin bytes.168
Descriptin f bt address pt n bytes.169
FLASH cnfiguratin prtectin.170
Prprietary cde readut prtectin(P CRP).177
Write prtectin errr(WRP ERR)
Prgramming sequence errr(PGS ERR)
Errr crrectin cde errr(S NEC CERR/DB ECC ERR) .
ptin byte change errr(PT CHANGE ERR) .
FLASH accesscntrl register(FLASH_ACR) .
FLASH key register fr bank 1(FLASH_KEY R 1) .
FLASH ptin key register(FLASH_PT KEY R) .
FLASH cntrl register fr bank 1(FLASH_CR 1) .
FLASH status register fr bank 1(FLASH_SR 1) .
FLASH clear cntrl register fr bank 1(FLASH_CCR 1)
FLASH ptin cntrl register(FLASH_PT CR) .
FLASH ptin status register(FLASH_PTS R_CUR) .
FLASH ptin status register(FLASH_PTS R_PRG) .
FLASH ptin clear cntrl register(FLASH_PT CCR) .
FLASH prtectin address fr bank 1(FLASH_PRAR_CUR 1) .
FLASH prtectin address fr bank 1(FLASH_PRAR_PRG 1) .
FLASH secure address fr bank 1(FLASH_SCAR_CUR 1) .
FLASH secure address fr bank 1(FLASH_SCAR_PRG 1) .
FLASH write sectr prtectin fr bank 1
(FLASH_WPS N_CUR1R) .
FLASH write sectr prtectin fr bank 1
(FLASH_WPS N_PRG1R) .209
FLASH register bt address FLASH_BT_CURR)
FLASH register bt address FLASH_BT_PR GR)
FLASH CRC cntrl register fr bank 1(FLASH_CRC CR 1) .
FLASH CRC start address register fr bank 1
(FLASH_CRCSADD1R) .
FLASH CRC end address register fr bank 1
(FLASH_CRCEADD1R) .
FLASH CRC data re gisler(FLASH_CRC DATA R)
FLASH ECC fail address fr bank 1(FLASH_ECC_FA1R) .
FLASH key register fr bank 2(FLASH_KEY R 2) .
FLASH cntrl register fr bank 2(FLASH_CR 2) .
FLASH status register fr bank 2(FLASH_SR 2) .
FLASH clear cntrl register fr bank 2(FLASH_CCR 2) .
FLASH prtectin address fr bank 2(FLASH_PRAR_CUR 2) .
FLASH prtectin address fr bank 2(FLASH_PRAR_PRG 2) . 223
FLASH secure address fr bank 2(FLASH_SCAR_CUR 2) .223
FLASH secure address fr bank 2(FLASH_SCAR_PRG 2) .1.224
FLASH write sectr prtec in fr bank 2
(FLASH_WPS N_CUR2R) .225
FLASH write sectr prtectin fr bank 2
(FLASH_WPS N_PRG2R) .225
FLASH CRC cntrl register fr bank 2(FLASH_CRC CR 2) .226
FLASH CRC start address register fr bank 2
(FLASH_CRCSADD2R) .227
FLASH CRC end address register fr bank 2
(FLASH_CRCEADD2R) .228
FLASH ECC fail address fr bank 2(FLASH_ECC_FA2R) .228
Pwer-n reset(PR) /pwer-dwn reset(PDR) .256
PWR cntrl status register 1(PWR_CSR 1) .
PWR D 3 dmain cntrl register(PWR_D3CR) .295
FLASH register map and reset values.
4.3.1Assciated features.
4.3.2Bt state machine.
4.3.3Secure access mde cnfiguratin.
4.4.1Secure area setting service.
4.4.2Secure area exiting service.
4.5.1Access rules.
4.5.2Setting secure user memry areas
Summary f Flash prtectin mechanisms.
5.3.1PWR pins and internal signals.
5.4.1System supply startup.
5.4.2Cre dmain.
5.4.3PWR ext em nal supply.
5.4.4Backup dmain.
5.4.5VB AT battery charging.
5.4.6Analg supply.
5.4.7USB regulatr.
Pwersupply supervisin.
5.5.1
5.5.2Brwn ut reset(B R) .
5.5.3Prgrammable vltage detectr(PVD) .
5.5.4Analg vltage detectr(AVD) ：
5.5.5Battery vltage threshlds.
5.5.6Tm perature threshlds.
Pwer management.
5.6.1perating mdes.
5.6.2Vltage scaling.
5.6.3Pwer cntrl mdes.
5.6.4Pwer management examples
Lw-pwer mdes，
5.7.1Slwing dwn system clcks.
5.7.2Cntrlling peripheral clcks.
5.7.3Entering lw-pwer mdes
5.7.4Exiting frm lw-pwer mdes.
5.7.5C Sleep mde.
5.7.6C Stp mde.
5.7.7D Stp mde.
5.7.8Stp mde.
5.7.9D Standby mde.
5.7.10Standby mde.
5.7.11Mnitring lw-pwer mdes.
PWR register descriptn.
5.8.1PWR cntrl register 1(PWR_CR 1) .
5.8.3PWR cntrl register 2(PWR_CR 2) .
5.8.4PWR cntrl register 3(PWR_CR 3) .
5.8.5PWR CPU cntrl register(PWR_CPU CR)
Secure internal Flashmemry(SI FM) .
4.1Intrductin
4.2Glssary·
4.3Secure access mde.
4.4Rt secure services(RSS) .
4.5Secure user sftware.
Pwer cntrl(PWR) .
5.1Intrductin
5.2PWR main features.
5.3PWR blck diagram.
5.4Pwer supplies.
STRM0433Rev 6
PWR wakeup clear register(PWR_WKU PCR) .
PWR wakeup flag register(PWR_WK UP FR) .
PWR wakeup enable and plarity register(PWR_WK UP EPR) . 297
PWR register map.298
Memry-t-peripheral transfer using LP UART 1 interface.
verall descriptn f the lw-pwer applicatin example based n
LP UART 1 transmissin.
Lw-pwer mde security reset(I pwr_rst.
Clck utput generatin(MC 1/MC 2) .
Hand lng clck generatrs in Stp and Standby mde.
CPU and bus matrix clck gating cntrl.
RCC Surce Cntrl Register(RCC_CR) .
RCC Inte mal ClckSurce Calibratin Register(RCC_ICS CR) . 371
RCC HSI cnfiguratin register(RCC_HSI CFG R) .
RCC Clck Recvery RC Register(RCC_CRRC R) .
RCC CSI cnfiguratin register(RCC_CSIC FGR) .
RCC Clck Cnfiguratin Register(RCC_CFG R) .
RCC Dmain 1 Clck Cnfiguratin Register(RCC_D1CFGR) . 378
RCC Dmain 2 Clck Cnfiguratin Register(RCC_D2CFGR) . 380
RCC Dmain 3 Clck Cnfiguratin Register(RCC_D3CFGR) . 381
RCC PLLs ClckSurce Selectin Register(RCC_PLLC KS ELR) . 382
RCC PLLs Cnfiguratin Register(RCC_PLLC FGR) .
RCC PLL 1 Dividers Cnfiguratin Register(RCC_PLL1DIVR) .
RCCPLL1Fracinal Divider Register(RCC_PLL1FRACR) .
RCC PLL 2 Dividers Cnfiguratin Register(RCC_PLL2DIVR) .
RCC PLL 2 Fractinal Divider Register(RCC_PLL2FRACR) .
RCC PLL 3 Dividers Cnfiguratin Register(RCC_PLL3DIVR) .
RCC PLL 3 Fractinal Divider Register(RCC_PLL3FRACR)
RCC Dmain 1 Kernel Clck Cnfiguratin Register
(RCC_D1CCIPR) .
RCC Dmain 2 Kernel Clck Cnf guratin Register
(RCC_D2CCIP1R) .
RCC Dmain 2 Kernel Clck Cnfiguratin Register
(RCC_D2CCIP2R) .
RCC Dmain 3 Kernel Clck Cnfiguratin Register
(RCC_D3CCIPR) .
RCC ClckSurce Interrupt Enable Register(RCC_CIE R) .
RCC ClckSurce Interrupt Flag Register(RCC_C IFR) .
Lw-pwer D 3 dmain.
6.1Intrduc in
6.3.4Alternate implementatins.
ther lw-pwer applicatins.
RCC main features.
RCC blck diagram.
RCC pins and inte mal signals.
RCC reset blck functinal descriptin
7.4.1Pwer-n/ff reset.
7.4.2System reset.
7.4.3Lcal resets.
7.4.4Reset surce identificatin.
7.4.6Backup dmain reset.
7.4.7Pwer-n and wakeup sequences.
RCC clck blck functinal descriptin
7.5.1Clck naming cnventin.
7.5.2scil atrs descriptin.
7.5.3Clck Security System(CSS) ：
7.5.5PLL descriptin.
7.5.6System clck(sys_ck) .
7.5.8Kernel clck selectin.
7.5.9General clck cncept verview
7.5.10Peripheral allcatin
7.5.11Peripheral clck gating cntrl.
RCC Interrupts.
RCC register descriptin.
7.7.1Register mapping verview.
RCC ClckSurce Interrupt Clear Register(RCC_CICR)
RCC Backup Dmain Cntrl Register(RCC_B DCR)
RCC Clck Cntrl and Status Register(RCC_CSR) .
RCCAHB3Reset Register(RCC_AHB3RSTR) .
RCCA HB 1 Peripheral Reset Register(RCC_AHB1RSTR) .
RCCA HB 2 Peripheral Reset Register(RCC_AHB2RSTR)
RCCA HB 4 Peripheral Reset Register(RCC_AHB4RSTR) ：
RCCA PB 3 Peripheral Reset Register(RCC_APB3RSTR) .
RCCA PB 1 Peripheral Reset Register(RCC_APB1LRSTR) .
RCCA PB 1 Peripheral Reset Register(RCC_APB1HRSTR)
RCCA PB 2 Peripheral Reset Register(RCC_APB2RSTR) .
RCCA PB 4 Peripheral Reset Register(RCC_APB4RSTR) .
RCC Glbal Cntrl Register(RCC_GCR) .
RC CD 3 Autnmus mde Register(RCC_D3AMR)
RCC Reset Status Register(RCC_RSR) .
RCCA HB 3 Clck Register(RCC_AHB3ENR) .
RCCA HB 1 Clck Register(RCC_AHB1ENR)
RCCA HB 2 Clck Register(RCC_AHB2ENR)
RCCA HB 4 Clck Register(RCC_AHB4ENR) .
RCCA PB 3 Clck Register(RCC_APB3ENR) .
RCCA PB 1 Clck Register(RCC_APB1LENR) .
RCCA PB 1 Clck Register(RCC_APB1HENR)
RCCA PB 2 Clck Register(RCC_APB2ENR) .
RCCA PB 4 Clck Register(RCC_APB4ENR) .
RCCA HB 3 Sleep Clck Register(RCC_AHB3LPENR) .
RCCA HB 1 Sleep Clck Register(RCC_AHB1LPENR)
RCCA HB 2 Sleep Clck Register(RCC_AHB2LPENR) .
RCCA HB 4 Sleep Clck Register(RCC_AHB4LPENR) .
RCCA PB 3 Sleep Clck Register(RCC_APB3LPENR) .
RCCAPB1Lw Sleep Clck Register(RCC_APB1LLPENR) .
RCCA PB 1 High Sleep Clck Register(RCC_APB1HLPENR) .
RCCA PB 2 Sleep Clck Register(RCC_APB2LPENR) -.
RCCA PB 4 Sleep Clck Register(RCC_APB4LPENR) .
Synchrnizatin input.
Frequency errr measurement.
Frequency errr evaluatin and autmatic trimming.
CRS initializatin and cnfiguratin.
CRS cntrl register(CRS_CR) .
CRS cnfiguratin register(CRS_CFG R) .
CRS interrupt and status register(CRS_IS R) .
CRS interrupt flag clear register(CRS_ICR) .
H SEM Write/Read/Read Lck register address.
H SEM register semaphre x(H SEM_Rx) .
H SEM read lck register semaphre x(H SEM_RL Rx) . 1
H SEM interrupt enable register(H SEM_IER) .
H SEM interrupt clear register(H SEM_ICR)
H SEM interrupt status register(H SEM_IS R) .
H SEM interrupt status register(H SEM_MISR) -
RCC register map.
CRS main features.
CRS functinal descriptin，
8.3.1CRS blck diagram.
CRS inte mal signals.
8.4.4 CR Slw-pwer mdes.
CRS interrupts.
CRS registers.
8.7.5CRS register map.
Hardware semaphre intrductin.
Hardware semaphre main features.
H SEM functinal descriptin
9.3.1H SEM b